The present invention relates to a semiconductor integrated circuit and an operation method of the same and, more particularly, relates to a technique useful to shorten the period of a DC offset cancelling operation.
A traditional superheterodyne receiver needs an image rejection filter for removing a wave interfering an image frequency accompanying frequency conversion. Japanese Unexamined Patent Publication No. 2001-211098 (patent document 1) discloses a technique of calibrating a DC offset of a baseband amplification signal caused by an LO (local) leak or the like in a direct conversion receiver which requires no image rejection filter as an external part. Specifically, an input of a variable gain amplifier is connected to an output of a reception mixer via a low-pass filter, an input of an analog-to-digital converter is connected to an output of the variable gain amplifier, an input of a control circuit is connected to an output of the analog-to-digital converter, an input of a digital-to-analog converter is connected to an output of the control circuit, and an output of the digital-to-analog converter is connected to an offset control input terminal of the variable gain amplifier. The control circuit measures a direct current offset of an output of the variable gain amplifier, so that the direct current offset of the output of the variable gain amplifier can be calibrated by the A/D conversion and the D/A conversion.
Japanese Unexamined Patent Publication No. 2005-12409 (patent document 2) discloses a technique of preventing the influence of a change in gain setting from being exerted on a posterior stage by connecting an offset suppressor on the input side of a gain controller, monitoring an output DC level of the gain controller by a DC feedback unit, and controlling the offset suppressor so that the monitored output DC level maintains a predetermined value.
Japanese Unexamined Patent Publication No. 2007-88983 (patent document 3) discloses a reception circuit of a direct-conversion-type OFDM reception circuit having a DC offset estimation circuit for extracting a DC component by a fast Fourier transform (FFT) circuit and estimating a DC offset amount, a D/A converter for converting the estimated DC offset amount into an analog value, and a subtractor for subtracting the DC offset estimation amount as the analog value from an output of a mixer so that clipping of a baseband signal at an input of an A/D converter is suppressed and a DC component can be demodulated without losing original information of a low-frequency component.
WO 2005/055450 (patent document 4) discloses a receiving apparatus which stops operation of a high-frequency circuit such as a low noise amplifier or a quadrature demodulator only in the case where the reception field intensity of an interfering wave input from the high-frequency circuit is considerably higher than that of a desired reception signal and there is the possibility that a receiver saturates due to the interfering wave during an offset voltage calibration period, and which always sets the operation state of the high-frequency circuit such as a low noise amplifier or a quadrature demodulator without changing the operation state in the case where there is no possibility that the receiver saturates due to the interfering wave input from the high-frequency circuit before and after the offset voltage calibration period.
Japanese Unexamined Patent Application Publication (Translation of PCT Application) No. 2009-552936 (patent document 5) discloses a technique of connecting a DC offset compensation circuit including a DC offset detection circuit, a digital-to-analog program register, and a digital-to-analog converter to an output of a filter gain stage configured by an operational amplifier as a basic component of a complex filter.